This work presents the implementation and metrological validation of a Million-Point Sparse Fourier Transform (MP-SFT) on a Xilinx RFSoC platform for high-resolution spectral analysis. As FFT-based methods become inefficient for a large number of points or sparse signals, the proposed system exploits inverse modulo permutations, windowed subsampling, and randomized hashing to reconstruct only the significant spectral components. A hybrid hardware-software architecture is adopted: the Programmable Logic (PL) performs real-time data acquisition and parallel subsampled FFT processing, while a host workstation executes the final reconstruction through de-hashing, voting, and amplitude estimation. A calibration procedure based on polynomial regression ensures accurate reconstruction across the [10], [951] MHz range. Performance was evaluated in terms of Spurious-Free Dynamic Range (SFDR) and accuracy. Experimental results show an SFDR up to 65.2 dB, limited mainly by a clock-related spur at 491.52MHz. The system exhibits reconstruction accuracy better than 0.08 dB for input amplitudes between -10 dBm and -40 dBm, confirming linearity and robustness. These results demonstrate the feasibility of hardware-accelerated sparse spectral estimation on heterogeneous platforms and provide a foundation for future extensions toward full hardware reconstruction and real-time analysis of adaptive or non-stationary signals.

Real-Time Implementation and Characterization of the Sparse Fourier Transform for Spectral Measurements

Balestrieri E.;De Vito L.;Picariello E.;Picariello F.;Rapuano S.;Tudosa I.
2026-01-01

Abstract

This work presents the implementation and metrological validation of a Million-Point Sparse Fourier Transform (MP-SFT) on a Xilinx RFSoC platform for high-resolution spectral analysis. As FFT-based methods become inefficient for a large number of points or sparse signals, the proposed system exploits inverse modulo permutations, windowed subsampling, and randomized hashing to reconstruct only the significant spectral components. A hybrid hardware-software architecture is adopted: the Programmable Logic (PL) performs real-time data acquisition and parallel subsampled FFT processing, while a host workstation executes the final reconstruction through de-hashing, voting, and amplitude estimation. A calibration procedure based on polynomial regression ensures accurate reconstruction across the [10], [951] MHz range. Performance was evaluated in terms of Spurious-Free Dynamic Range (SFDR) and accuracy. Experimental results show an SFDR up to 65.2 dB, limited mainly by a clock-related spur at 491.52MHz. The system exhibits reconstruction accuracy better than 0.08 dB for input amplitudes between -10 dBm and -40 dBm, confirming linearity and robustness. These results demonstrate the feasibility of hardware-accelerated sparse spectral estimation on heterogeneous platforms and provide a foundation for future extensions toward full hardware reconstruction and real-time analysis of adaptive or non-stationary signals.
2026
FPGA
MP-SFT
RFSoC
Sparse Fourier Transform
Spectral Analysis
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.12070/77265
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